You executed the following code: BEGIN DBMS_SCHEDULER.SET_ATTRIBUTE ( NAME => ’JOB_A’, ATTRIBUTE => ’JOB_PRIORITY’, VALUE => 7); END; / After analyzing the above code, what conclusion will you draw?()
Because of a power outage, instance failure has occurred. From what point in the redo log does recovery begin and where does it end?()
You issued the following block of code: SQL>BEGIN DBMS_RESOURCE_MANAGER_PRIVS.GRANT_SWITCH_CONSUMER_GROUP( ’PROG_ROLE’, ’DEVELOPERS’ ,FALSE); END; SQL>/ Which option is NOT a result of executing the above code?()
What is the correct order of steps to perform an online database backup?() a. alter database begin backup b. alter database end backup c. Back up the database datafiles d. Back up the archive log files e. alter system switch logfile
Consider the following code snippet: BEGIN DBMS_SCHEDULER.SET_ATTRIBUTE ( name => ,,lne_job1, attribute => ,,job_priority, value => 1); END; / If this code were executed, which of the following statements would be true?()
简述T-SQL语言中Begin„End语句的作用。
Because of a power outage, instance failure has occurred. From what point in the redo log does recovery begin and where does it end? ()
写出下面程序段的执行结果: Declare @m int,@n int Select @m=0, @n=0 While @m<30 Begin Set @n=@n+3 Set @m=@m+@n End Select @m, @n
矩阵\\(A=\\begin{bmatrix}0&1&3&2\\\\0&4&-1&3\\\\0&0&2&1\\\\0&5&-4&3\\end{bmatrix}\\),则\\(A\\)的秩为______
绘制五角红星程序的编辑与运行。 程序代码如下: from turtle import * color('red','red') begin_fill() for i in range(5): fd(200) rt(144) end_fill() done() 要求上传程序编辑窗口截屏和运行结果窗口截屏图片。 注意:上传截图要清晰。
下面T-SQL代码运行完的结果是(选一项)declare @counter intset @counter=1while @counter<3beginset @counter=@counter+1print @counterbreakprint 'loop'end()
在下面给出的PL/SQL代码块中,()行代码会导致失败。 1 DECLARE 2 vNum NUMBER : - 100; 3 BEGIN 4 vNum - vNum / 10; 5 END
已知时钟信号clkin的频率为100MHz的方波信号,下面程序中clk1信号的占空比为()。 module function(rst, clkin, clk1); input clkin, rst; output clk1; reg[2:0] m, n; reg clk1; always @(posedge clkin) begin if(!rst) begin clk1<=0; m<=0; end else begin if(m==4) m<=0; else m<=m+1; if(m<2) clk1<=1; else clk1<=0; end end endmodule
设计一个能将四位二进制数转换成两个BCD码的电路,模块名为_4bits2bcd,如果要完成设计,在(1)处应填写()选项的代码。 module _4bits2bcd(Bin,BCD1,BCD0); input[3:0] Bin; output[3:0] BCD1,BCD2; reg [3:0] BCD1,BCD0; always@(Bin) begin {BCD1,BCD0}=8'h00; if(Bin<10) begin (1) end else begin (2) end end endmodule
描述下面代码的功能。 module func (reset,clk,out); input clk,reset; output reg out; reg [2:0] count; always @(posedge clk, reset) begin if(~reset) begin count<=0; end else begin if(count="=5)"> A、5分频电路
8、基于initial语句产生普通时钟信号, parameter clk_period = 10; reg clk; initial begin clk = 0; ________________; end
阻塞赋值在一个begin-end块中表现为串行行为。
请改正下面程序中存在的错误。 def deco(func): def inner(): print(&39;deco begin&39;) func() print(&39;deco end&39;) return inner @deco def add(a,b): print(a+b) if __name__==&39;__main__&39;: add(3,5)
接上题,阅读下列关于秒计数模块的代码,下列说法正确的是()。 always @(posedge clk or posedge reset) begin if(reset==1'b1) begin {s_h,s_l}<=8'h00; else begin if(flag==1'b1) begin if(s_l==4'd9) begin s_l<=4'd0; if(s_h==4'd5) begin s_h<=4'd0; end else s_h<=s_h+1'b1; end else begin s_l<=s_l+1'b1; end end end end
4、两个并发进程P1和P2的程序代码在下面给出。其中,A、B、C、D、E均为原语。 P1: begin P2: Begin A; D; B; E; C; End; End; P1和P2进程以不可预知的速度推进,它们可能的执行过程有 。 (1)A→B→C→D→E (2)A→B→E→D→C (3)A→B→D→C→E (4)A→D→C→E→B (5)A→D→B→C→E (6)A→D→E→B→C (7)D→E→A→B→C (8)D→A→C→E→B (9)D→A→B→E→C (10)D→A→E→B→C
38、已知某verilog仿真测试文件时钟信号描述如下: parameter PERIOD = 10; always begin CLK = 1'b0; (PERIOD/2) CLK = 1'b1; (PERIOD/2); end 且该verilog文件顶部有如下代码:`timescale 1us / 1ns,则模拟仿真时钟周期是
走马灯控制信号输出采用了一段式状态机建模方法。参考代码如下: always @(posedge clk_1) if(!rst) begin state<=first; Q0<='b011; Q1<='b010; Q2<='b010; Q3<='b001; Q4<='b000; Q5<='b111; Q6<='b110; Q7<='b101; end else case(state) first:begin state<=second; Q0<='b101; Q1<='b011; Q2<='b010; Q3<='b010; Q4<='b001; Q5<='b000; Q6<='b111; Q7<='b110; end second:begin state<=third; Q0<='b110; Q1<='b101; Q2<='b011; Q3<='b010
4、用PV操作解决读者写者问题的正确程序如下: begin S, Sr: Semaphore; rc: integer; S:=1; Sr:=1; rc:=0; cobegin PROCESS Reader i (i=1,2,…) begin P(Sr); rc:=rc+1; if rc=1 then P(S); V(Sr); read file; P(Sr); rc:=rc-1; if rc=0 thenV(S); V(Sr) end; PROCESS Writer j (j=1,2,…) begin P(S); Write file; V(S) end; coend; end; 请回答: (1) 信号量 Sr的作用; (2) 程序中什么语句用于读写互斥,写写互斥; (3) 若规定仅允许5个进程同时读怎样修改程序?
下面硬件描述语言实现的电路逻辑功能是什么?可选答案为: module Test2(Clk,nRst,iTRIG,oTRIG); input Clk,nRst,iTRIG; output oTRIG; reg[7:0] cnt; reg DY1; parameter DY_time = 8'H09; always@(posedge Clk or negedge nRst) begin if (!nRst) DY1 = 0; else if (iTRIG ) DY1 = 1; else if (cnt >= DY_time) DY1 = 0; end always@(posedge Clk or negedge nRst) begin if (!nRst) cnt <=0; else if (DY1 = = 1 ) cnt <= cnt + 1; else cnt <=0; end assign oTRIG =DY1; endmodule